Memory Loading
Rules
Memory must be installed in pairs - modules (2 DIMMs of equal density)
Memory modules (pairs of DIMMS) are available in three densities: 4 GB (2×2048MB), 8
GB (2×4096MB), and 16 GB (2×8192MB).
Memory bundle product numbers consist of DIMMS already qualified in the memory
modules.
Minimum memory is 2 GB per cell
Maximum memory per system is 256 GB-using sixteen 16 GB memory modules (8 GB
pairs) per system.
Larger DIMMs must be loaded first across a cell, followed by progressively smaller DIMM
sizes.
On each cell board, Memory Pairs must be installed in the following order:
(0A, 0B), (1A, 1B), (2A, 2B), (3A, 3B), (4A, 4B), (5A, 5B), (6A, 6B),(7A, 7B)
DIMM mixing other than recommended configurations is supported as long as the
memory loading rules are followed
rx7640 Recommended Memory Configurations
Memory
per Cell
(GBs)
Number of DIMMs
Quad Echelon
2 GB 4 GB 8 GB
2 1 3 0 2 1 3 0
OA, OB
1A, 1B 2A, 2B 3A, 3B 4A, 4B 5A, 5B 6A, 6B 7A, 7B
4 2
2 GB
8 4
2 GB 2 GB
16 8
2 GB 2 GB 2 GB 2 GB
32 16
2 GB 2 GB 2 GB 2 GB 2 GB 2 GB 2 GB 2 GB
32
8
4 GB 4 GB 4 GB 4 GB 2 GB 2 GB 2 GB 2 GB
64
16
4 GB 4 GB 4 GB 4 GB 4 GB 4 GB 4 GB 4 GB
64
8
8 GB 8 GB 8 GB 8 GB 4 GB 4 GB 4 GB 4 GB
128
16
8 GB 8 GB 8 GB 8 GB 8 GB 8 GB 8 GB 8 GB
Performance Tuning
Guidelines
For best performance, a cell should be configured with a multiple of eight DIMMs or four
pairs (although the server will execute properly with an odd number of pairs). It takes
eight DIMMs to populate both memory buses. Populating only one of the two memory
buses on a cell board will deliver only half the peak memory bandwidth.
Load memory equally across the available cell boards.
Memory Latencies
There are two types of memory latencies within the HP Integrity rx7640 Server:
1. Memory latency
within
the cell refers to the case where an application either runs on a
partition that consists of a single cell or uses cell local memory.
2. Memory latency
between
cells refers to the case where the partition consists of two cells and
cell interleaved memory is used. In this case 50% of the addresses are to memory on the same
cell as the requesting processor, and the other 50% of the addresses are to memory of the
other cell.
The HP Integrity rx7640 Server average memory latency depends on the number of CPUs in
the partition. Assuming that memory accesses are equally distributed across all cell boards and
memory controllers within the partition, the average idle memory latency (load to use) is as
show below:
QuickSpecs
HP Integrity rx7640 Server
Configuration
DA - 12470 Worldwide QuickSpecs — Version 25 — 5/8/2009
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