HP Series 7 Uživatelská příručka
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- Strana / 186
- Tabulka s obsahem
- KNIHY
- 7 Series FPGAs 1
- SelectIO Resources 1
- Revision History 2
- Table of Contents 5
- UG471 (v1.5) May 15, 2015 10
- About This Guide 11
- Preface: About This Guide 12
- New Features 14
- 7 Series FPGA I/O Bank Rules 17
- Introduction 19
- Xilinx DCI 20
- DCIRESET Primitive 22
- DCI Cascading 22
- DCI and 3-state DCI (T_DCI) 28
- DCI Usage Examples 31
- IBUF and IBUFG 35
- IBUF_IBUFDISABLE 35
- IBUF_INTERMDISABLE 36
- IBUFDS and IBUFGDS 36
- IBUFDS_DIFF_OUT_IBUFDISABLE 37
- IBUFDS_IBUFDISABLE 37
- IBUFDS_INTERMDISABLE 38
- IBUFDS_DIFF_OUT_INTERMDISABLE 38
- IOBUF_DCIEN 39
- IOBUF_INTERMDISABLE 40
- IOBUFDS_DCIEN 41
- IOBUFDS_DIFF_OUT 42
- IOBUFDS_DIFF_OUT_DCIEN 43
- IOBUFDS_INTERMDISABLE 44
- DCI_CASCADE Constraint 46
- Location Constraints 47
- IOSTANDARD Attribute 47
- IBUF_LOW_PWR Attribute 47
- Output Slew Rate Attributes 48
- VCCAUX_IO Constraint 50
- LVTTL (Low Voltage TTL) 51
- LVCMOS (Low Voltage CMOS) 54
- LVDCI _ DV2 57
- HSLVDCI (High-Speed LVDCI) 59
- HSTL_ I and HSTL_ I_18 60
- HSTL_I_12 60
- HSTL_ II and HSTL_ II_18 60
- N/A Available 62
- External Termination 63
- Differential HSTL Class I 64
- HSTL Class II 66
- Differential HSTL Class II 68
- Not 3-stated 72
- (T pin logic Low) 72
- 3-stated 72
- (T pin logic High) 72
- SSTL18_I, DIFF_SSTL18_I 76
- DIFF_SSTL135 76
- User Guide for details 77
- HSUL_12 and DIFF_HSUL_12 84
- Example Board Topology 85
- Differential HSUL_12 86
- MOBILE_DDR (Low Power DDR) 88
- Transmitter Termination 91
- Receiver Termination 91
- Differential Clock 93
- Input to the FPGA 93
- BLVDS (Bus LVDS) 96
- Table 1-55: V 99
- Chapter 1: SelectIO Resources 102
- SelectIO Logic Resources 105
- ILOGIC Resources 106
- ZHOLD_DELAY 108
- OPPOSITE_EDGE Mode 109
- SAME_EDGE Mode 110
- SAME_EDGE_PIPELINED Mode 110
- Input DDR Resources (IDDR) 111
- ILOGIC Timing Models 112
- Clock Event 4 113
- Clock Event 1 113
- Clock Event 9 114
- IDELAYE2 Primitive 115
- IDELAY Ports 116
- IDELAYRESOLUTION 117
- IDELAY Attributes 118
- IDELAY Modes 119
- IDELAY Timing 120
- Clock Event 2 121
- Clock Event 3 121
- Clock Event 0 122
- IDELAYCTRL 123
- IDELAYCTRL Timing 124
- IDELAYCTRL Locations 124
- OLOGIC Resources 125
- Output DDR Overview (ODDR) 126
- Clock Forwarding 127
- Output DDR Primitive (ODDR) 128
- OLOGIC Timing Models 128
- Timing Characteristics 129
- ODELAYE2 Primitive 133
- ODELAY Ports 134
- ODELAY Attributes 136
- ODELAY Modes 137
- ODELAY Timing 138
- Chapter 3 141
- ISERDESE2 143
- Primitive 143
- Registered Outputs – Q1 to Q8 144
- Combinatorial Output – O 145
- Bitslip Operation - BITSLIP 145
- High-Speed Clock Input - CLK 146
- High-Speed Clock Input - CLKB 146
- Divided Clock Input - CLKDIV 146
- Oversampling Mode - OCLK 147
- Reset Input - RST 147
- ISERDESE2 Attributes 148
- DATA_RATE Attribute 149
- DATA_WIDTH Attribute 149
- INTERFACE_TYPE Attribute 149
- ISERDESE2 Clocking Methods 150
- MEMORY Interface Type 151
- MEMORY_QDR Interface Type 151
- OVERSAMPLE Interface Type 151
- ISERDESE2 Width Expansion 153
- OSERDESE2 154
- BITSLIP Submodule 156
- After Clock Event 3 158
- OSERDESE2 Primitive 160
- Data Path Output - OQ 161
- DATA_RATE_OQ Attribute 163
- DATA_RATE_TQ Attribute 163
- SERDES_MODE Attribute 164
- TRISTATE_WIDTH Attribute 164
- OSERDESE2 Width Expansion 165
- Output Feedback 166
- OSERDESE2 Latencies 166
- IO_FIFO Overview 171
- FIFO Core 172
- 7 Entries Deep 172
- Register Register 172
- IN_FIFO Primitive 173
- Table 3-15: IN_FIFO Ports 174
- OUT_FIFO 175
- OUT_FIFO Primitive 176
- Table 3-18: OUT_FIFO Ports 177
- Resetting the IO_FIFO 178
- EMPTY and FULL Flags 178
- Termination Options for 181
- SSO Noise Analysis 181
- TMDS_33 Far 3.3V 50Ω 183
- IO Standard 183
- Default Termination 183
Shrnutí obsahu
7 Series FPGAs SelectIO ResourcesUser GuideUG471 (v1.5) May 15, 2015
10 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015
100 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesLVTTL HR 3.3 3.3 N/A N/AMINI_LVDS
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 101UG471 (v1.5) May 15, 2015Rules for Combining I/O Standards in the Same BankTable 1-56,
102 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesHSLVDCI_15 HP N/A N/A Yes Driver
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 103UG471 (v1.5) May 15, 2015Rules for Combining I/O Standards in the Same BankMINI_LVDS_25
104 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSimultaneous Switching OutputsDue
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 105UG471 (v1.5) May 15, 2015Chapter 2SelectIO Logic ResourcesIntroductionThis chapter desc
106 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesILOGIC ResourcesThe ILOGIC
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 107UG471 (v1.5) May 15, 2015ILOGIC ResourcesX-Ref Target - Figure 2-3Figure 2-3: ILOGICE2
108 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesILOGIC can support the foll
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 109UG471 (v1.5) May 15, 2015ILOGIC ResourcesThe ILOGIC block registers have a common synch
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 11UG471 (v1.5) May 15, 2015PrefaceAbout This GuideXilinx® 7 series FPGAs include three uni
110 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesSAME_EDGE ModeIn the SAME_E
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 111UG471 (v1.5) May 15, 2015ILOGIC ResourcesInput DDR Resources (IDDR)Figure 2-8 shows the
112 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesIDDR VHDL and Verilog Templ
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 113UG471 (v1.5) May 15, 2015ILOGIC Resources• At time TIDOCK before Clock Event 1, the inp
114 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesClock Event 9• At time TISR
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 115UG471 (v1.5) May 15, 2015Input Delay Resources (IDELAY)IDELAYE2 PrimitiveFigure 2-11 sh
116 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesIDELAY PortsData Input from
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 117UG471 (v1.5) May 15, 2015Input Delay Resources (IDELAY)Pipeline Register Reset - REGRST
118 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesIDELAY AttributesTable 2-5
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 119UG471 (v1.5) May 15, 2015Input Delay Resources (IDELAY)IDELAY_TYPE AttributeThe IDELAY_
12 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Preface: About This Guide
120 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesIDELAYCTRL primitive must b
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 121UG471 (v1.5) May 15, 2015Input Delay Resources (IDELAY)Figure 2-12 shows an IDELAY (IDE
122 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesClock Event 0Before LD is p
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 123UG471 (v1.5) May 15, 2015IDELAYCTRLIn VHDL, each template has a component declaration s
124 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesRDY - ReadyThe ready (RDY)
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 125UG471 (v1.5) May 15, 2015OLOGIC ResourcesIDELAYCTRL Usage and Design GuidelinesFor more
126 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesThis section of the documen
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 127UG471 (v1.5) May 15, 2015OLOGIC ResourcesOPPOSITE_EDGE ModeIn OPPOSITE_EDGE mode, both
128 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesOutput DDR Primitive (ODDR)
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 129UG471 (v1.5) May 15, 2015OLOGIC ResourcesTiming CharacteristicsFigure 2-21 illustrates
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 13UG471 (v1.5) May 15, 2015Chapter 1SelectIO ResourcesI/O Tile OverviewInput/output charac
130 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesClock Event 4At time TOSRCK
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 131UG471 (v1.5) May 15, 2015OLOGIC ResourcesFigure 2-23 illustrates the OLOGIC 3-state reg
132 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesFigure 2-24 illustrates IOB
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 133UG471 (v1.5) May 15, 2015Output Delay Resources (ODELAY)—Not Available in HR BanksOutpu
134 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesODELAY PortsData Input from
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 135UG471 (v1.5) May 15, 2015Output Delay Resources (ODELAY)—Not Available in HR BanksPipel
136 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesODELAY AttributesTable 2-14
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 137UG471 (v1.5) May 15, 2015Output Delay Resources (ODELAY)—Not Available in HR BanksODELA
138 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic Resourcesthe FPGA logic. When LD is
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 139UG471 (v1.5) May 15, 2015Output Delay Resources (ODELAY)—Not Available in HR BanksClock
14 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesNew FeaturesThe 7 series devices s
140 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 2: SelectIO Logic ResourcesStability after an Incremen
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 141UG471 (v1.5) May 15, 2015Chapter 3Advanced SelectIO Logic ResourcesIntroductionThe I/O
142 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesISERDESE2 contains
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 143UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)ISERDESE2
144 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesISERDESE2 PortsReg
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 145UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)Combinator
146 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesWhen NUM_CE = 1, t
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 147UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)Serial Inp
148 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesISERDESE2 Attribut
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 149UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)DATA_RATE
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 15UG471 (v1.5) May 15, 2015SelectIO Resources IntroductionSelectIO Resources IntroductionA
150 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesNUM_CE AttributeTh
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 151UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)The only v
152 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resourcesin this mode. The
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 153UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)MEMORY_DDR
154 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resources4. The SLAVE uses
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 155UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)Using D an
156 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resourcesnames do not chang
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 157UG471 (v1.5) May 15, 2015Input Serial-to-Parallel Logic Resources (ISERDESE2)a shift ri
158 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesBitslip Timing Mod
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 159UG471 (v1.5) May 15, 2015Output Parallel-to-Serial Logic Resources (OSERDESE2)Output Pa
16 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesX-Ref Target - Figure 1-2Figure 1-
160 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resources3-State Parallel-t
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 161UG471 (v1.5) May 15, 2015Output Parallel-to-Serial Logic Resources (OSERDESE2)OSERDESE2
162 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resources3-state Control Ou
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 163UG471 (v1.5) May 15, 2015Output Parallel-to-Serial Logic Resources (OSERDESE2)OSERDESE2
164 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesDATA_WIDTH Attribu
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 165UG471 (v1.5) May 15, 2015Output Parallel-to-Serial Logic Resources (OSERDESE2)OSERDESE2
166 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesTable 3-9 lists th
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 167UG471 (v1.5) May 15, 2015Output Parallel-to-Serial Logic Resources (OSERDESE2)OSERDESE2
168 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesTiming Characteris
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 169UG471 (v1.5) May 15, 2015Output Parallel-to-Serial Logic Resources (OSERDESE2)Timing Ch
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 17UG471 (v1.5) May 15, 2015SelectIO Resources General GuidelinesSelectIO Resources General
170 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesClock Event 4Betwe
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 171UG471 (v1.5) May 15, 2015IO_FIFO OverviewClock Event 2The data bit E appears at OQ one
172 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesThe IO_FIFOs have
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 173UG471 (v1.5) May 15, 2015IO_FIFO Overview• 4 x 8 mode – This mode configures the FIFO t
174 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesTable 3-15 lists t
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 175UG471 (v1.5) May 15, 2015IO_FIFO OverviewOUT_FIFOThe OUT_FIFO is co-located with the IN
176 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resourcesused when the outp
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 177UG471 (v1.5) May 15, 2015IO_FIFO OverviewTable 3-18 lists the available ports in the OU
178 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic ResourcesResetting the IO_F
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 179UG471 (v1.5) May 15, 2015IO_FIFO Overview.Table 3-19: IO_FIFO AttributesAttribute Value
18 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSupply Voltages for the SelectIO P
180 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 3: Advanced SelectIO Logic Resources
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 181UG471 (v1.5) May 15, 2015Appendix ATermination Options for SSO Noise AnalysisThe PlanAh
182 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Appendix A: Termination Options for SSO Noise AnalysisLVCMOS (
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 183UG471 (v1.5) May 15, 2015Figure A-1 illustrates each of these terminations.TMDS_33 Far
184 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Appendix A: Termination Options for SSO Noise AnalysisX-Ref Ta
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 185UG471 (v1.5) May 15, 2015
186 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Appendix A: Termination Options for SSO Noise Analysis
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 19UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksThere is a
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com UG471 (v1.5) May 15, 2015The information disclosed to you hereunder (the "Materials&q
20 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO Resourcesimpedance due to process variation
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 21UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksFor control
22 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesDCIRESET PrimitiveDCIRESET is a Xi
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 23UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksFigure 1-7
24 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesThe guidelines when using DCI casc
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 25UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksControlled
26 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSplit-Termination DCI (Thevenin Eq
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 27UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksFigure 1-11
28 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesDCI and 3-state DCI (T_DCI)The cla
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 29UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksThe I/O sta
UG471 (v1.5) May 15, 2015 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide07/20/2012 1.2(Cont’d)Updated ILOGIC Resources. In Table 2-3, add
30 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesTo correctly use DCI in 7 series d
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 31UG471 (v1.5) May 15, 20157 Series FPGA DCI—Only available in the HP I/O banksDCI Usage E
32 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesX-Ref Target - Figure 1-14Figure 1
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 33UG471 (v1.5) May 15, 2015Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM
34 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO Resources7 Series FPGA SelectIO PrimitivesT
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 35UG471 (v1.5) May 15, 20157 Series FPGA SelectIO PrimitivesMore information including ins
36 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesIBUF_INTERMDISABLEThe IBUF_INTERMD
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 37UG471 (v1.5) May 15, 20157 Series FPGA SelectIO PrimitivesIBUFDS_DIFF_OUT and IBUFGDS_DI
38 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesThe IBUFDS_IBUFDISABLE primitive c
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 39UG471 (v1.5) May 15, 20157 Series FPGA SelectIO PrimitivesIBUFDISABLE port that can be u
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com UG471 (v1.5) May 15, 201505/13/2014 1.4(Cont’d)Added to list of criteria after Table 1-44.
40 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSplit-Termination DCI (Thevenin Eq
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 41UG471 (v1.5) May 15, 20157 Series FPGA SelectIO PrimitivesThe IOBUF_INTERMDISABLE primit
42 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesThe IOBUFDS_DCIEN primitive can di
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 43UG471 (v1.5) May 15, 20157 Series FPGA SelectIO PrimitivesIOBUFDS_DIFF_OUT_DCIENThe IOBU
44 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO Resourcessplit-termination DCI feature, thi
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 45UG471 (v1.5) May 15, 20157 Series FPGA SelectIO Primitives(IN_TERM) for more details on
46 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesOBUFTThe generic 3-state output bu
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 47UG471 (v1.5) May 15, 20157 Series FPGA SelectIO Attributes/ConstraintsCONFIG DCI_CASCADE
48 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO Resources•All VREF-based inputs such as HSL
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 49UG471 (v1.5) May 15, 20157 Series FPGA SelectIO Attributes/ConstraintsThe DRIVE attribut
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 5UG471 (v1.5) May 15, 2015Revision History . . . . . . . . . . . . . . . . . . . . . . . .
50 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesInternal VREFThe VREF for an I/O b
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 51UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsIn Verilog, the Verilog
52 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesFigure 1-37 shows unidirectional t
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 53UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-38 shows a bid
54 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesLVCMOS (Low Voltage CMOS)LVCMOS is
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 55UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-40 shows a bid
56 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesTable 1-14 details the allowed att
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 57UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsLVDCI _ DV2A controlled
58 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesThere are no optional current driv
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 59UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsHSLVDCI (High-Speed LVD
6 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015IOBUFDS_DIFF_OUT . . . . . . . . . . . . . . . . . . . . . . . .
60 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesHSTL (High-Speed Transceiver Logic
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 61UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsHSTL_ II_DCI and HSTL_
62 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesDifferential HSTL can also be used
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 63UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsX-Ref Target - Figure 1
64 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesDifferential HSTL Class IFigure 1-
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 65UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-48 shows a sam
66 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesHSTL Class IIFigure 1-49 shows a s
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 67UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-50 shows a sam
68 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesDifferential HSTL Class IIFigure 1
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 69UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-52 shows a sam
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 7UG471 (v1.5) May 15, 2015SSTL18, SSTL15, SSTL135, SSTL12 . . . . . . . . . . . . . . . .
70 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesFigure 1-53 shows a sample circuit
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 71UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-54 shows a sam
72 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesHSTL_II_T_DCI (1.5V or 1.8V) Split
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 73UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-56 shows a sam
74 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSSTL (Stub-Series Terminated Logic
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 75UG471 (v1.5) May 15, 2015Supported I/O Standards and Terminationsbidirectional signals (
76 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSSTL15_R, SSTL135_R, DIFF_SSTL15_R
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 77UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsNote: A lower resistanc
78 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSSTL18, SSTL15, SSTL135, SSTL12Fig
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 79UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-58 shows a sam
8 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Combinatorial Output Data and 3-State Control Path . . . . . .
80 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesDifferential SSTL18, SSTL15, SSTL1
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 81UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-60 shows a sam
82 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesFigure 1-61 shows a sample circuit
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 83UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-62 shows a sam
84 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesSSTL18, SSTL15, SSTL135, or SSTL12
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 85UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsHSUL_DCI_12 and DIFF_HS
86 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesFigure 1-65 shows a sample circuit
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 87UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsFigure 1-67 shows a sam
88 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesFigure 1-69 shows a sample circuit
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 89UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsTable 1-40: IOSTANDARD
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 9UG471 (v1.5) May 15, 2015ISERDESE2 Feedback from OSERDESE2 . . . . . . . . . . . . . . .
90 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesTable 1-41: IOSTANDARD Attributes
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 91UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsLVDS and LVDS_25 (Low V
92 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesFigure 1-71 is an example of a dif
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 93UG471 (v1.5) May 15, 2015Supported I/O Standards and Terminations• The differential sign
94 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesRSDS (Reduced Swing Differential S
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 95UG471 (v1.5) May 15, 2015Supported I/O Standards and TerminationsPPDS (Point-to-Point Di
96 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesBLVDS (Bus LVDS)Since LVDS is inte
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 97UG471 (v1.5) May 15, 2015Rules for Combining I/O Standards in the Same BankRules for Com
98 www.xilinx.com 7 Series FPGAs SelectIO Resources User GuideUG471 (v1.5) May 15, 2015Chapter 1: SelectIO ResourcesTable 1-55, summarizes the VCCO an
7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 99UG471 (v1.5) May 15, 2015Rules for Combining I/O Standards in the Same BankDIFF_SSTL18_I
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