HP B160L Uživatelský manuál stáhnout pdf (Strana 12)

PA-RISC Processors

2.2 PA-RISC Processors

2.2.1 Introduction

The PA-RISC processors are RISC processors from HP, started in the early 1980s as a replacement for

different platforms used in HP computers and developed until the early 2000s. Three major revisions

of the PA-RISC architecture were developed:

1. 32-bit MMU-less (no virtual memory) PA-RISC 1.0, implemented in several early processors and

used in the very ﬁrst PA-RISC servers;

2. 32-bit PA-RISC 1.1, used in the large range of PA-7x00 processors, and HP 9000 servers and

workstations from the late-1980s and 1990s;

3. 64-bit PA-RISC 2.0, which extended the 32-bit PA-RISC 1.1 to 64-bit width in the PA-8x00

processors and featured a redesign of most parts of the architecture, used in the late-1990s and

2000s in the last PA-RISC computers.

Almost all HP Unix systems from the mid-1980 until the early 2000s were based on PA-RISC — other

HP product lines (as the HP 3000 systems) and few external integrators (OEMs) used PA-RISC proces-

sors as well.

There are roughly ﬁve main classes of actual PA-RISC processor designs — two PA-RISC 1.0, two

PA-RISC 1.1 and one PA-RISC 2.0, with individual processors mostly being iterations of these basic

designs.

 TS-1, the ﬁrst PA-RISC processor, PA-RISC 1.0 32-bit, implemented in TTL.

 NS-1, NS-2 and PCX, the PA-RISC 1.0 32-bit sucessors. NS-2 tweaked the NS-1 design (both

implemented in NMOS) and PCX implemented the NS-2 design on CMOS.

 PA-7000 and PA-7100, the ﬁrst PA-RISC 1.1 processors, and the later PA-7100LC and PA-

7300LC, integrated “low-cost” PA-RISC 1.1 processors, all 32-bit. The former two have VSC

bus system interfaces, with the PA-7000 being the more-integrated descendant of the earlier PCX

and the PA-7100 adding superscalarity and integrating the FPU. The two LC processors inte-

grate additional processing logic and direct GSC system bus attachments and on-die memory

controllers. The PA-7300LC extended the original PA-7100LC design with true on-chip cache

and modiﬁed memory controller and bus interfaces.

 PA-7200, a high-performance PA-RISC 1.1 32-bit processor, a rather large redesign and the ﬁrst

PA-RISC processor with Runway bus interface.

 PA-8000 and PA-8200, the ﬁrst PA-RISC 2.0 64-bit processors, were very similar.

The subsequent 64-bit processors all were iterations of the basic PA-8000 core.

PA-8500, PA-8600 and PA-8700 are direct evolutions of the PA-8000 with large on-chip caches.

The PA-8600 and PA-8700 are slight modiﬁcations of the PA-8500 with different cache layouts

and process technologies.

PA-8800 and PA-8900 implemented dual PA-8700 cores onto single-dies with large off-die but

on-chip caches.

Several third-party vendors designed and produced PA-RISC processors under license, including the

general-purpose CPUs from Hitachi (PA/50 and HARP) and various microcontrollers from Winbond

and Oki.

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HP B160L Uživatelský manuál Strana 12