HP 16501A LOGIC Uživatelský manuál stáhnout pdf (Strana 24)

To find the nth assertion of a chip select line

1 Select the timing analyzer Trigger menu.

2 Define the glitch/edge1 term to represent the asserting transition on

the chip select line.

You can rename the Edge1 term to make it correspond more closely to the

problem domain, for example, to CHIP_SEL.

Under Timing Sequence Levels, enter the following sequence

specification:

TRIGGER on “CHIP_SEL” 10 times

Triggering on the 10th Assertion of a Chip Select Line

Triggering

To find the nth assertion of a chip select line

1–14

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 129 130

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HP 16501A LOGIC Uživatelský manuál Strana 24